In general, as a semiconductor device is scaled down, property variation of a MOS transistor is getting larger according to skew and temperature since it is difficult to control device parameters and manufacturing processes which determine the performance of the MOS transistor. For instance, the manufacturing processes and device parameters include width and length of a transistor gate, thickness of a gate oxide, and a seat resistor and so on. As the size of the transistor is smaller, target values of those parameters become lower and, thus, tolerance to a target value of each process increases and the property variation of the transistor also becomes larger. Therefore, it is preferable that circuits within the semiconductor device are designed to operate without being effected by the variation of the transistor due to the skew and temperature. However, it is getting difficult to design circuits that have immunity from the increasing variation of the transistor.